1. Field of the Invention
The present invention relates to semiconductor memory devices. More particularly, the present invention relates to an efficient and a fast SRAM circuit and method providing for read, modify, and write operations in a single clock cycle time.
2. Background Information
A conventional Static Random Access Memory (SRAM) is a form of electronic data storage which retains data as long as power is supplied. Random access means that locations in the memory can be written to or read from in any order, regardless of the memory location that was last accessed. SRAM memory is widely utilized in electronic devices, and is particularly well-suited for use in portable or hand-held applications where low power consumption is required. SRAM memory is also used in high performance applications such as microprocessor caching since the SRAM can provide fast access times while not requiring the cell data refresh operations (as required in a Dynamic Random Access Memory).
FIG. 1 illustrates a conventional system 100 for implementing testing in memory devices, wherein the conventional system comprises SRAM and an external adder performing read, modify, and write operations while utilizing multiple clock cycle times. The conventional system 100 comprises a static random access memory (SRAM) block 104 coupled to an application specific integrated circuit (ASIC) block 102, wherein the read operations are initiated by asserting Read port select bar (RPSb) and write operations are initiated by asserting Write port select bar (WPSb). A RPSb port 123 of the SRAM block 104 is coupled to an RPSb port 103 of the ASIC block 102, a WPSb port 125 of the SRAM block 104 is coupled to a WPSb port 105 of the ASIC block 102. A Byte write select bar (BWSb) port 127 of the SRAM block 104 is coupled to a BWSb port 107 of the ASIC block 102. An address input pin (A) 121 of the SRAM block 104 is coupled to an address input pin 101 of the ASIC block 102. The Data OUT pin 109 and Data IN pin 111 of the ASIC block 102 are coupled to the D pin 129 and the Q pin 131 of the SRAM block 104, respectively. A positive input clock signal (K) 115 and a negative input clock signal Kbar 117 (also be referred to as Kb) of the ASIC block 102 are coupled to the positive input clock signal (K) 137 and the negative input clock signal (Kb) 135 of the SRAM block 104. A clock input signal (CQ/CQbar) 133 of the SRAM block 104 are coupled to a clock input signal (CLKIN/CLKINb) 113 of the ASIC block 102.
Referring to FIG. 2, a timing diagram 200 illustrates all operation of the conventional system 100. Waveform 201 shows a clock cycle comprising read, modify and write sub cycles. Waveform 203 shows incremental operations of the external adder. Waveform 205 shows the incremented data, which is updated to an address in the memory.
The operational steps of the timing diagram 200 are described as follows. In a first step, the SRAM is reset. In a second step, data is read from SRAM. In a third step, data is incremented through an external adder. In a fourth step, new data is written back in to the SRAM. Thus, multiple clock sub cycles are required for performing read, modify and write operations, which is a disadvantage in the conventional system.
During the testing of circuits, such as a conventional Analog to Digital converter (ADC), the number of times a particular converter output value has been hit is detected and a SRAM circuit is used for accumulation of data from the ADC circuit. In order to accumulate data in the SRAM circuit, first the previous accumulated data is read from the SRAM, and then data is incremented by one externally, and then rewritten back into the SRAM circuit to the same address location.
A disadvantage of the conventional method is that the SRAM block 104 cannot perform increment or decrement operations internally, hence the increment and decrement operations are done externally by the ASIC block 102. The process requires read, write and modify operations to complete one increment operation, which requires multiple clock cycles, thereby increasing the testing time. Another disadvantage of conventional method is that an extra circuit and an extra SRAM is required for overflow protection, thereby adding to die area and adding to the power consumption.
It would be desirable to provide an improved circuit providing a fast and efficient SRAM circuit with no additional circuit for overflow protection, thus performing the read, modify and write operations in a single clock cycle time.